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Reduced instruction set computing
Results: 261

#	Item
11	RISC-V on Sakura-G Advisor(s): Thomas Unterluggauer Institute for Applied Information Processing and Communications (IAIK) Graz University of Technology, Austria Motivation Add to Reading List Source URL: www.iaik.tugraz.at Language: English - Date: 2015-09-08 06:00:03 Instruction set architectures Reconfigurable computing Fabless semiconductor companies Xilinx Field-programmable gate array RISC-V Reduced instruction set computing
12	Capability Hardware Enhanced RISC Instructions: CHERI Instruction-Set Architecture Add to Reading List Source URL: www.cl.cam.ac.uk Language: English - Date: 2015-12-01 06:21:41 Instruction set architectures Central processing unit Computer architecture Memory management Memory protection Capability-based security Pointer MIPS instruction set 64-bit computing Instruction set Reduced instruction set computing Kernel
13	MonetDB/X100: Hyper-Pipelining Query Execution Peter Boncz, Marcin Zukowski, Niels Nes CWI Kruislaan 413 Amsterdam, The Netherlands {P.Boncz,M.Zukowski,N.Nes}@cwi.nl Add to Reading List Source URL: www-db.cs.wisc.edu Language: English - Date: 2011-09-16 15:44:48 Central processing unit Relational database management systems Instruction set architectures Cross-platform software MonetDB Structured storage Column-oriented DBMS Pipeline CPU cache Optimizing compiler Vector processor Reduced instruction set computing
14	The Newsletter of the Wakefield RISC OS Computer Club For all users of the Acorn and RISC OS family of computers Add to Reading List Source URL: www.wrocc.org.uk Language: English - Date: 2016-04-03 05:02:22 Computer architecture Software Computing Single-board computers Linux-based devices Microcontrollers ARM architecture Personal computers RISC OS Raspberry Pi RiscPC Reduced instruction set computing
15	Everybody be cool, this is a roppery! Vincenzo Iozzo zynamics GmbH Tim Kornau zynamics GmbH Add to Reading List Source URL: www.trailofbits.com Language: English - Date: 2016-04-15 11:36:17 Computing Computer architecture Computer engineering Central processing unit Return-oriented programming Instruction set Processor register Machine code Reduced instruction set computing Gadget Subroutine Stack machine
16	Low-Cost Software Countermeasures Against Fault Attacks: Implementation and Performances Trade Offs Alessandro Barenghi Luca Breveglieri Add to Reading List Source URL: euler.ecs.umass.edu Language: English - Date: 2011-03-24 10:57:36 Computer architecture Computing Computer engineering Central processing unit Computer memory Instruction set architectures Cache Advanced Encryption Standard CPU cache Side-channel attack ARM architecture Reduced instruction set computing
17	USING INFORMATION THEORY TO STUDY THE EFFICIENCY AND CAPACITY OF COMPUTERS AND SIMILAR DEVICES Boris Ryabko Institute of Computational Technology of Siberian Branch of Russian Academy of Science Siberian State University Add to Reading List Source URL: sp.cs.tut.fi Language: English - Date: 2010-08-12 11:09:05 MMIX Computer MIX Reduced instruction set computing Assembly language Sequence Instruction set Computer architecture Donald Knuth Computing
18	An Overview of Static Pipelining Ian Finlaysony , Gang-Ryung Uhz , David Whalleyy and Gary Tysony y Department of Computer Science z Department of Computer Science Add to Reading List Source URL: www.cs.fsu.edu Language: English - Date: 2011-08-10 14:26:43 Central processing unit Compiler optimizations Instruction set architectures Classes of computers Software pipelining Instruction pipeline MIPS architecture Reduced instruction set computing Transport triggered architecture Computer architecture Computer engineering Computer hardware
19	Improving Low Power Processor Efficiency with Static Pipelining Ian Finlayson† , Gang-Ryung Uh‡ , David Whalley† and Gary Tyson† † ‡ Add to Reading List Source URL: www.cs.fsu.edu Language: English - Date: 2011-01-31 11:18:06 Central processing unit Compiler optimizations Classes of computers Instruction set architectures Software pipelining Instruction pipeline Reduced instruction set computing MIPS architecture Microarchitecture Computer architecture Computing Computer engineering
20	Adapting Compilation Techniques to Enhance the Packing of Instructions into Registers Stephen Hines, David Whalley, Gary Tyson Computer Science Department Florida State University Tallahassee, FL Add to Reading List Source URL: www.cs.fsu.edu Language: English - Date: 2006-08-24 08:01:51 Compiler optimizations Assembly languages Instruction scheduling Reduced instruction set computing Instruction set Branch predication Register renaming Very long instruction word Addressing mode Computer architecture Computing Computer engineering